The present invention relates to a thin film transistor substrate having low resistive and chemical resistant electrode interconnections and a method of forming the same.
In recent years, scaled up and high fine liquid crystal displays utilizing thin film transistors have been required. A display has been practiced which has a screen size of over 10 inches and a pixel pitch less than 0.24 mm.
FIG. 1 is a circuit diagram illustrative of a liquid crystal display utilizing thin film transistors. A plurality of gate bus interconnections 9 are provided in vertical to a plurality of source bus interconnections 16. Thin film transistors 30 serving as switching devices are provided at crossing points of the gate bus interconnections 9 and the source bus interconnections 16. If in the plural gate bus interconnections 9, a gate bus interconnection Xi is selected, then the thin film transistors 30 connected to the gate bus interconnection Xi turn ON so that voltage signals corresponding to the information about an image are transmitted from the source to the drain.
The drain is connected to a pixel electrode 25. The voltage signal is then transmitted to the pixel electrode 25. The pixel electrode 25 and an opposite electrode 27 make a pair, which sandwiches a liquid crystal layer 26 to apply an electric field across the liquid crystal layer 26 so as to vary light transmission of the liquid crystal layer 26.
On the other hand, if the gate bus interconnection Xi enters into nonselected state, then the thin film transistors 30 connected to the gate bus interconnection Xi turn OFF. Subsequently, a gate bus interconnection Xj is selected, then the thin film transistors 30 connected to the gate bus interconnection Xj turn ON. After the gate has turned OFF, a voltage between the pixel electrode 25 and the opposite electrode 27 is kept by the liquid crystal layer 26 until the same gate bus interconnection is selected.
By the way, the scaling up of the fine liquid crystal display results in an increase in length of the interconnection whilst reduction in width of the interconnection. As a result, the resistance of the interconnection is increased. The time delay in transmission of the signal on the interconnection is defined by a time constant given by the product of the resistance of the interconnection and the parasitic capacitance thereof. The increase in the resistance of the interconnection causes an increase of the time constant, resulting in an increase in the time delay in transmission of the signal on the interconnection. There is caused deterioration in rising up and falling down of the signal. This makes it difficult that the signals are transmitted within a predetermined time duration.
In order to settle the above problem, it is required to reduce the resistance of the interconnection. To reduce the resistance of the interconnection, it is possible to increase the thickness of the interconnection. This increase in thickness of the interconnection causes a deterioration in step coverage of the interconnection layer and insulative films which overly the edge of the interconnection. As a result, there are caused disconnection of the interconnection layer at the edge of the gate interconnection layer with the increased thickness or deterioration in insulation property of the insulative film at the step.
To avoid the above problem, it is required to use a low resistive metal interconnection such as aluminum, molybdenum and tungsten interconnections. Notwithstanding, such low resistive metal has a weak acidic resistance for which reason the low resistive metal may show corrosion by etchant including a hydrochloric acid and a nitric acid to be used for forming the pixel electrode 25.
The above low resistive metal also has a weak chemical resistance so that such metal may be dissolved into various chemicals such as developer, resist release solution and cleaning solution. This results in a deterioration in property of such chemicals.
In order to solve the above problem, the following technique was proposed as disclosed in the Japanese laid-open patent publication No. 3-72319. FIG. 2 is a fragmentary plane view illustrative of a conventional transistor substrate. FIG. 3 is a fragmentary cross sectional elevation view along B--B line in FIG. 2.
As illustrated in FIG. 2, this conventional thin film transistor has a gate bus interconnection 67 which comprises a first gate bus interconnection 65 and a second gate bus interconnection 66. The second gate bus interconnection 66 is formed to cover the first gate bus interconnection 65 completely. A gate electrode 62 of the thin film transistor 39 is branched from the second gate bus interconnection 66. A pixel electrode 25 is connected via a drain electrode 64 to the thin film transistor 39.
As illustrated in FIG. 3, a gate electrode 62 is provided over a glass substrate 1 wherein the gate electrode 62 is branched from a second gate bus interconnection 66. A gate insulation film 10 made of silicon nitride is formed over an entire surface of the glass substrate 1 to cover the gate electrode 62. A semiconductor layer 11 made of amorphous silicon is formed on the gate insulation film 10 over the gate electrode 62. A contact layer 12 made of n-amorphous silicon is formed over the semiconductor layer 11. The contact layer 12 is provided to form ohmic contact between the semiconductor layer 11 and source and drain electrodes 63 and 64. The source electrode 63 is formed to be branched from the source bus interconnection 61. A pixel electrode 25 is superimposed on an edge of the drain electrode 64.
In the above prior art, the first gate bus interconnection is made of a low resistive metal. The second gate bus interconnection made of a highly acidic-resistive metal such as tantalum is formed to cover the first gate bus interconnection completely so as to prevent corrosion by etchant of the first gate bus interconnection and to reduce the gate bus electric resistance. The second gate bus interconnection protects the first gate bus interconnection from etchant and from being dissolved into chemicals in photo-lithography process.
In the above prior art, however, there is a problem that when the first gate bus interconnection 65 is formed, the low resistive metal is dissolved into the chemicals for photolithography.
The method of forming the interconnection structure in the well known photo-lithography will be described with reference to FIGS. 4A through 4D.
With reference to FIG. 4A, a metal film 38 is formed on a thin film transistor substrate 31. A photo-resist film 34 is applied on the metal film 38.
With reference to FIG. 4B, the photo-resist film 34 is subjected to an exposure and development for patterning the same into the interconnections wherein the developer is used as an etchant to the resist film 34. The developer is made into contact with a top surface of the metal film 38.
With reference to FIG. 4C, the metal film 38 is etched by use of the photo-resist film 34 as a mask to form interconnections.
With reference to FIG. 4D, the photo-resist film 34 is removed by use of a resist release solution where the resist release solution is made into contact with the top and side surfaces of the metal film 38.
Further, the cleaning process is required before entry into the following step. Namely, the metal film 38 is further made into contact with the cleaning solution.
As described above, in the photo-lithography process, three chemicals are used other than the etchant and are made into contact with the metal film 38. If in order to reduce the resistivity of the interconnection, low resistive metals such as aluminum alloy, aluminum, molybdenum and tungsten are used, then their metals are dissolved into the chemicals which are alkyl thereby deterioration in properties of the chemicals. This results in a lowering of the yield of the products.
As to forming the interconnections of the gate bus 67 illustrated in FIG. 2, a first photo-lithography process is carried out to form the first gate bus interconnection 65 and subsequently a second photo-lithography process is carried out to form the second gate bus interconnection 66. Namely, two photo-lithography processes are necessary. Different resist film masks are provided for two times exposures and developments, resulting in lowering the yield and increase in the manufacturing cost. This also makes it difficult to form fine liquid crystal display.
The resistance of the source bus interconnection 61 is not reduced. If the screen size is over 13 inches, not only a delay of gate signal but also deterioration of source signal are not ignore, for which reason it is required to reduce the resistance of the source bus interconnection.
In order to solve the above problem, there was proposed a technique using aluminum as a low resistive metal which is disclosed in the Japanese laid-open patent publication No. 4-240824.
In this technique, a simple photo-lithography process is carried out to form a chemical resistive film which covers the top and side faces of the low resistive electrode interconnection. FIG. 5 is a fragmentary cross sectional elevation view illustrative of the conventional thin film transistor
As illustrated in FIG. 5, a first gate electrode film 3 made of aluminum is formed on a glass substrate 1. A gate electrode film 4 comprising a metal film made of at least one selected from the group consisting of tantalum, niobium, tungsten, molybdenum and alloys thereof is deposited for subsequent patterning of the first gate film 3 and the second gate film 4 to form interconnections. In a pure water at a temperature in the range of 70-100.degree. C., a heat treatment is carried out to form a third gate electrode film 5 made of aluminum oxide only on side faces of the first gate electrode film 3 to thereby form a gate electrode 2.
In the above prior art, if the second gate electrode film 4 is made of tantalum, then tantalum and aluminum oxide films with sufficient chemical resistance cover the top and side faces of the first gate electrode film 3 made of low resistive metal, for example, aluminum to prevent the first gate electrode film 3 from corrosion by etchant and from being dissolved into chemicals to be used in the photo-lithography process.
However, when the second gate electrode 4 and the first gate electrode 3 are patterned to form the interconnections by the photolithography, the aluminum may be dissolved into the chemicals to be used in the photo-lithography whereby the property of the chemicals are deteriorated.
Also this technique can not be applied in forming the source bus interconnection 16 and the source electrode 20. Notwithstanding, the first source bus interconnection 13 and the first source electrode 14, both of which are made of aluminum, are covered by the second source bus interconnection 17 and the second source electrode film 18, both of which are made of metal highly resistive to chemicals. Also the first drain electrode film 21 made of aluminum is covered by the second drain electrode film 22 made of the metal highly resistive to chemicals. The top of the semiconductor layer 11 is covered by a channel protection film 28.
However, in the above structure of the liquid crystal display, the side faces of the aluminum film are shown and may be made contact into the chemicals for which reason the aluminum is dissolved into the chemicals.
If the pixel electrode 29 is made of a tin-added indium oxide, then the pixel electrode 29 and the first drain electrode 21 comprising the aluminum film are exposed to the alkyl resist release solution and cleaning solution in the photo-lithography process, then a local battery system via an electrolytic solution between the aluminum and tin-added indium oxide, resulting in a corrosion of the aluminum film.
There was proposed a technique that a chemical resistant metal film covers the interconnections, which is disclosed in the Japanese laid-open patent publication No. 1-94664. The tungsten interconnection is coated by the tungsten nitride film as illustrated in FIG. 6.
Over a silicon substrate 41, a gate insulation film 43 is provided which extends across source and drain regions 47 and 48. A potential barrier layer 44 made of tungsten nitride and having a thickness of 50 nanometers is formed over the gate insulation film 43. A tungsten layer 45 having a thickness of 400 nanometers is laminated over the potential barrier layer 44. Further, a tungsten nitride layer 46 having a thickness of 50 nanometers is provided to cover the top and side faces of the tungsten layer 45 to thereby form the gate electrode.
In the above technique, a refractory metal nitride layer with a low reactivity to silicon atom is provided to coat the refractory metal layer forming the gate electrode in order to prevent deterioration in withstand voltage caused by the reaction of the gate electrode or the inter-layer insulator to the gate electrode and the refractory metal layer and also prevent variation in threshold voltage of the transistor.
In the above prior art technique, the tungsten nitride films 44 and 46 highly resistive to the chemicals are provided to coat entirely the gate electrode. If this structure is applied to the thin film transistor, then it is possible to suppress the low resistive metal from being dissolved into the chemicals in the photo-lithography and from the corrosion of the electrode by the etchant.
In the above prior art, however, the tungsten layer may be dissolved into the chemicals in the photo-lithography whereby the priority of the chemicals is deteriorated. The tungsten layer 45 and the tungsten nitride layer 46 are formed by two times of the photo-lithography processes, whereby the number of processes is increased and it is difficult to form fine elements.
Further, the above technique has a problem that the silicon oxide film as the gate Insulation film 43 is not adhesive to the tungsten nitride film 44.
In the foregoing prior art, the low resistive and poor chemical resistant metal layers are exposed to chemicals used for photo-lithography in forming the rich chemical resistant metal layers which cover the low resistive and poor chemical resistant metal layers and may be dissolved into the chemicals, even the low resistive and poor chemical resistant metal layers will completely be coated by the rich chemical resistant metal layers, for which reason the properties of the chemicals are deteriorated.
In order to form the chemical resistant interconnections which cover the low resistive poor chemical resistant interconnections, two time photo-lithography processes are required to be carried out. This results in increase in the number of processes and makes it difficult to form the fine elements.